1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a thyristor.
2. Description of the Related Art
Production of a 90-nm generation of SRAMs (Static Random Access Memories) has been starting since the second half of 2004. However, development of a next 65-nm generation of SRAMs is faced with an SRAM crisis in which problems such as an increase in leakage current, a decrease in operation margin and the like become noticeable and circuit design becomes extremely difficult. Accordingly, new SRAMs for superseding a 6Tr-SRAM in the past are being actively studied.
An SRAM using a thyristor, that is, a Thyristor RAM (hereinafter denoted as a TRAM) is one of promising candidates for superseding the 6Tr-SRAM in the past. A thyristor is basically formed by joining a first p-type semiconductor layer, a first n-type semiconductor layer, a second p-type semiconductor layer, and a second n-type semiconductor layer in order. An anode electrode is connected to the first p-type semiconductor layer provided in an end part, and a cathode electrode is connected to the second n-type semiconductor layer provided in an end part on the other side. An example has been reported in which high-speed operation is made possible by forming a gate electrode having a MOS structure on a second p-type semiconductor layer disposed between a first n-type semiconductor layer and a second n-type semiconductor layer in a configuration of the thyristor (see U.S. Pat. No. 6,462,359 referred to as Patent Document 1 hereinafter, for example).
When a TRAM as described above is formed within a semiconductor substrate, the size of a memory cell is generally defined by an impurity profile in a depth direction. While the introduction of an impurity into a semiconductor substrate has heretofore been performed by ion implantation, consideration is given to a technique of forming an n-type semiconductor layer and a p-type semiconductor layer on a semiconductor substrate while introducing an impurity by epitaxial growth, for purposes of forming a steeper impurity profile and reducing the area of a memory cell.
As a TRAM as described above, as shown in a schematic configuration sectional view of FIG. 8, there is a TRAM having a first n-type semiconductor layer n1 and a first p-type semiconductor layer p1 laminated in this order on a second p-type semiconductor layer p2 disposed on the surface side of a semiconductor substrate 11. In a case of manufacturing such a TRAM, the first n-type semiconductor layer n1 including an n-type impurity of arsenic (As) is formed by epitaxial growth on the second p-type semiconductor layer p2 on one side of a gate electrode 13 provided on the semiconductor substrate 11 with a gate insulating film 12 interposed between the gate electrode 13 and the semiconductor substrate 11. Next, the first p-type semiconductor layer p1 including a p-type impurity of boron (B) is formed on the first n-type semiconductor layer n1 by epitaxial growth. In addition, a second n-type semiconductor layer n2 including an n-type impurity of As is formed by epitaxial growth on the second p-type semiconductor layer p2 on another side of the gate electrode 13.